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ASAHI
KASEI
[AK2305]
AK2305
Dual PCM CODEC for ISDN TERMINAL ADAPTER
GENERAL DESCRIPTION
AK2305 is a dual PCM CODEC-Filter most suitable for ISDN Terminal Adapter. A-law/ulaw is selected by the internal register. In addition to CODEC, this device has dual DTMF receiver and External Tone Input pin. Input/output operational amplifiers included in this device are used for transmit/receive gain adjustment. AK2305 has internal volume control to attenuate signal from 0dB to -12dB by 3dB step control which is defined by an internal register written through the serial interface. PCM interface of AK2305 accepts several clock formats, which are Long Frame, Short Frame, GCI, IDL. 64k-4096kHz clock input is available for PCM interface.
-
FEATURE
Dual PCM CODEC and Filtering systems for ISDN Terminal Adapter Dual DTMF Receiver External Tone Input(AUX) Independent functions on each channel - Frame Sync Signal(8kHz) - Power Down Mode(Pin/Register operation) - Mute(Pin/Register operation) - Gain Adjustment: 0 to -12dB (3dB step) Selectable PCM Data Interface Timing: Long Frame / Short Frame / GCI / IDL Variable PCM Data Rate: 64k x N [Hz] (64k - 4.096 M H z) Operational Amplifier for Gain Adjustment A-law/u-law Register Selectable Serial Interface Power on Reset Single +5V 5% CMOS technology Low Power Consumption (85mW typ)
-
PACKAGE
- 48LQFP 9.0 x 9.0 mm (0.5mm pin pitch)
C0029-E-02
1
1999/8
ASAHI
KASEI
[AK2305]
CONTENTS
ITEMS
PAGE
- BLOCK DIAGRAM............................................. 3 - PIN ASSIGNMENT............................................. 4 - PIN CONDITION................................................ 5 - PIN FUNCTION................................................. 6 - CIRCUIT DESCRIPTION...................................... 8 - FUNCTIONAL DESCRIPTION.............................. 9 - PCM INTERFACE...................................... 9 LONGFRAME/SHORTFRAME................ 10 GCI.................................................... 12 IDL..................................................... 13 RESET............................................... 14 - POWER DOWN........................................ 15 - MUTE.................................................... 17 - GAIN ADJUSTMENT................................. 18 - DTMF RECEIVER.................................... 19 - TONE GENERATOR................................. 21 - AUX INPUT............................................. 21 - SERIAL INTERFACE................................ 22 - REGISTER....................................................... 25 - ABSOLUTE MAXIMUM RATINGS......................... 28 - RECOMMENDED OPERATING CONDITIONS........ 28 - ELECTRICAL CHARACTERISTICS....................... 28 - APPLICATION CIRCUIT EXAMPLE.......................39 - PACKAGE INFORMATION.................................. 42
C0029-E-02
2
1999/8
ASAHI
KASEI
[AK2305]
BLOCK DIAGRAM
GSX0 47 VFX0 48
AMPT0
VR0T
AAF0
CODEC CH0
PCM I/F
29 33
VRX0 VFR0 GSR0
1 2 3
VR0R
AMPR0
S1 SMF0 S2 S3
DX0 DR0 26 FS0
27
BCLK
GSX1 14 VFX1 13
AMPT1
VR1T
AAF1
S4 S5 SMF1 S6
CODEC CH1
28 32 25
VRX1 12 VFR1 11 GSR1 10 TNOUT 9 VREF
4
VR1R
AMPR1
DX1 DR1 FS1
TONEGEN0
S7 S8 S9
22 21 8 18 17
TNOE0 TNOE1 AUX MUTE0 MUTE1 DTO00-03 DTO10-13
VRTN
TONEGEN1
BGREF
4 4 4
37-40
DTIN0
46
DTMF Receiver0 DTMF Receiver1
4
24 STD0 41-44
DTIN1 15 AVDD 6 AVSS 7 DVDD 31 DVSS 30
45 16
23 STD1 20 DTOE
PLL
Internal Register
Serial I/F
35 SCLK 34 DATA 36 CS 19 PD
5
TST1 TST2
LPC
C0029-E-02
3
1999/8
ASAHI
KASEI
[AK2305]
PIN ASSIGNMENT
FS1 FS0 BCLK DX1 DX0 DVSS DVDD DR1 DR0 DATA SCLK CS 25 26 27 28 29 30 31 32 33 34 35 36
DTO00 DTO01 DTO02 DTO03 DTO10 DTO11 DTO12 DTO13 TST1 DTIN0 GSX0 VFX0 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 STD0 STD1 TNOE0 TNOE1 DTOE PD MUTE0 MUTE1 TST2 DTIN1 GSX1 VFX1
12 11 10 9 8 7 6 5 4 3 2 1 VRX1 VFR1 GSR1 TNOUT AUX AVSS AVDD LPC VREF GSR0 VFR0 VRX0
C0029-E-02
4
1999/8
ASAHI
KASEI
[AK2305]
PIN CONDITION
Pin# Name I/O Pin type AC load (MAX.) DC load (MIN.)
Outout status (Power down mode) Output status (Reset)
Remarks
VRX0 50pF 1 O Analog Hi-Z Hi-Z 10k VFR0 2 I Analog GSR0 50pF 3 O Analog Hi-Z Hi-Z 10k (*1) VREF 4 O Analog external cap LPC 5 O Analog external cap AVDD 6 AVSS 7 AUX 8 I Analog TNOUT 50pF 9 O Analog Hi-Z Hi-Z 10k GSR1 50pF 10 O Analog Hi-Z Hi-Z 10k (*1) VFR1 11 I Analog VRX1 50pF 12 O Analog Hi-Z Hi-Z 10k VFX1 13 I Analog GSX1 50pF 14 O Analog Hi-Z Hi-Z 10k (*1) DTIN1 15 I Analog TST2 I TTL Factory use only 16 MUTE1 17 I TTL MUTE0 18 I TTL PD 19 I TTL DTOE 20 I TTL TNOE1 21 I TTL TNOE0 22 I TTL STD1 15pF 23 O CMOS L L STD0 15pF 24 O CMOS L L FS1 25 I TTL (*2) FS0 26 I TTL BCLK 27 I TTL DX1 15pF 28 O CMOS Hi-Z Hi-Z DX0 15pF 29 O CMOS Hi-Z Hi-Z DVSS 30 DVDD 31 DR1 32 I TTL (*3) DR0 33 I TTL DATA 15pF 34 I/O TTL/CMOS Input Input SCLK 35 I TTL CSN 36 I TTL DTO00 15pF 37 O CMOS Hi-Z Hi-Z DTO01 15pF 38 O CMOS Hi-Z Hi-Z DTO02 15pF 39 O CMOS Hi-Z Hi-Z DTO03 15pF 40 O CMOS Hi-Z Hi-Z DTO10 15pF 41 O CMOS Hi-Z Hi-Z DTO11 15pF 42 O CMOS Hi-Z Hi-Z DTO12 15pF 43 O CMOS Hi-Z Hi-Z DTO13 15pF 44 O CMOS Hi-Z Hi-Z TST1 I TTL Factory use only 45 DTIN0 46 I Analog GSX0 50pF 47 O Analog Hi-Z Hi-Z 10k (*1) VFX0 48 I Analog *1) DC load(MIN.) includes a feedback resistance of input/output op-amp. *2) Pulled down to VSS in GCI/IDL mode. *3) Pulled down to VSS in 2ch Multiplex mode.
C0029-E-02
5
1999/8
ASAHI
KASEI
[AK2305]
PIN FUNCTION
Pin# 48 47 1 2 3 10 11 12 14 13 29 Name VFX0 GSX0 VRX0 VFX0 GSR0 GSR1 VFR1 VRX1 GSX1 VFX1 DX0 I/O I O O I O O I O O I O Function Transmit analog input. Inverting input of transmit gain adjustment amplifier for channel 0. Output of transmit gain adjustment amplifier for channel 0. Receive analog output of SMF for channel 0. This output can drive 10k and 50pF. Transmit analog input. Inverting input of transmit gain adjustment amplifier for channel 0. Output of receive gain adjustment amplifier for channel 0. Output of receive gain adjustment amplifier for channel 1. Inverting input of receive gain adjustment amplifier for channel 1. Receive analog output of SMF for channel 1. This output can drive 10k and 50pF. Output of transmit gain adjustment amplifier for channel 1. Transmit analog input. Inverting input of transmit gain adjustment amplifier for channel 1. Serial output of PCM data of ch0. In Long Frame / Short Frame mode, output PCM data of ch0. In GCI / IDL mode, output PCM data of ch0 is multiplexed with ch1. The PCM data rate is synchronized with BCLK. See "PCM INTERFACE" from page 9. This output remains in the high impedance state except for the period of transmitting PCM data. Serial input of PCM data of ch0. In Long Frame / Short Frame mode, input PCM data of ch0. In GCI / IDL mode, input PCM data of ch0 is multiplexed with ch1. The PCM data rate is synchronized with BCLK. See "PCM INTERFACE" from page 9. Serial output of PCM data of ch1. In Long Frame / Short Frame mode, output PCM data of ch1. The PCM data rate is synchronized with BCLK. See "PCM INTERFACE" from page 9. This output remains in the high impedance state except for the period of transmitting PCM data. In 2ch multiplexd mode, this pin remains in the high impedance state. Serial input of PCM data of ch1. In Long Frame / Short Frame mode, input PCM data of ch1. The PCM data rate is synchronized with BCLK. See "PCM INTERFACE" from page 9. In GCI / IDL mode, this pin is pulled down to VSS. Frame sync input for channel 0. FS0 must be 8KHz clock synchronized in BCLK.
33
DR0
I
28
DX1
O
32
DR1
O
26
FS0
I
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6
1999/8
ASAHI
Pin# 25
KASEI
Name FS1 I/O I
[AK2305]
Function Frame sync input for channel 1. FS1 must be 8KHz clock synchronized in BCLK. In GCI / IDL mode, this pin is pulled down to VSS. Bit clock of PCM data interface. This clock is apply for both ch0 and ch1. BCLK should be synchoronized with 8 x N kHz(FSn x N kHz). DTMF tone input of ch 0. Output of DTMF receiver 0. DTO00 is LSB.
27 46 37 38 39 40 24 15 41 42 43 44 23 20 22 21 8 9 34 35 36 18 17 19 5 4 31 30 6 7 45 16
BCLK DTIN0 DTO00 DTO01 DTO02 DTO03 STD0 DTIN1 DTO10 DTO11 DTO12 DTO13 STD1 DTOE TNOE0 TNOE1 AUX TNOUT DATA SCLK
CS
I I O O O O O I O O O O O I I I I O I/O I I I I I O O I I
Steering to delay output of ch0. After the DTMF decoding, latch is renewed and this output alters to high level. DTMF tone input. Output of DTMF receiver 1. DTO10 is LSB.
the output
MUTE0 MUTE1 PD LPC VREF DVDD DVSS AVDD AVSS TST1 TST2
Steering to delay output of ch0. After the DTMF decoding, the output latch is renewed and this output alters to high level. Output enable pin for the DTMF receiver. Output enable pin for the tone generator 0. Output enable pin for the tone generator 1. External tone input pin. Input signal should be through more than 0.1uF of an external capacitance. Tone output pin. Data input of serial interface. Clock input of serial interface. Read and write enable of serial interface. Active high input for ch0 mute. Active high input for ch0 mute. Active high input for all power down. Pin for PLL loop filter. Connect to AVSS with 0.22uF or larger. Analog ground output. To stabilize the analog ground, connect to AVSS with 0.1uF or larger. Digital positive supply voltage. System digital +5V supply. Digital negative supply voltage. System digital ground. Analog positive supply voltage. Systems analog +5V supply. Analog negative supply voltage. System analog ground. Only for factory use. Should to be fixed to DVSS.
C0029-E-02
7
1999/8
ASAHI
KASEI
[AK2305]
CIRCUIT DESCRIPTION
Block AMPT0,1 Function Op-amp for input gain adjustment. This op-amp is used as an inverting amplifier. Adjusting the gain with external resistors. The resistor larger than 10k is recommended for the feedback resistor. AMP0(1) becomes automatically power down, when both CODEC ch0(1) and DTMFR0(1) are power down. Op-amp for output gain adjustment. This op-amp is used as an inverting amplifier. Adjusting the gain with external resistors. The resistor larger than 10k is recommended for the feedback resistor. Integrated anti-aliasing filter which prevents signals around the sampling rate from folding back into the voice band. AAF is a 2nd order RC low-pass filter. Converts analog signal to 8bit PCM data according to the companding schemes of ITU recommendation G.711; A-law or u-law. The band limiting filter is also integrated. The selection of companding schemes is set by ALAWN register as follows: "H": u-Law "L": A-Law Expands 8bit PCM data according to A-law or u-law. The selection of companding schemes is set by ALAWN register as follows: "H": u-Law "L": A-Law Extracts the inband signal from D/A output. It also corrects the sinx/x effect of D/A output. Provides the stable analog ground voltage (2.4V) using an on-chip band-gap reference circuit which is temperature compensated. Generates two kinds of tone; 400Hz and 1300Hz. Tone selection is defined by registers. ON/OFF of tone output is controlled by TNOE0/1. Controls output signals from VRX0, VRX1, TNOUT pins. Each switch is controlled by register. Detects and decodes the DTMF tone. ON/OFF of decoded output is controlled by DTOE. Gain selects of analog I/O signals. It is posibble to select gain from 0dB to -12dB (3dB/step* 5steps). Gain is defined by register. Interface to internal register by using SCLK, DATA, and CS pins. 1word=14bit; Instruction code: 2bit, address: 3bit, data: 9bit(1dummy bit included). PLL generates system clock of AK2305. Reference clock is FSn (8KHz). More than 0.22uF of an external capacitance should be connected between LPC and AVSS. PCM data rate is available for 64xN(N = 1 to 64)kHz which synchronizes with BCLK. Data format is selected in four types(Long Frame, Short Frame, GCI, IDL). 2ch PCM data are interfaced through DR0,1 and DX0,1 in non multiplexed mode or DR0 and Dx0 in multiplexed mode.
AMPR0,1
AAF A/D
D/A
SMF BGREF TONE GEN 0 TONE GEN 1 SWITCH Sn(n=1-9) DTMF Receiver0,1 VR0T/R VR1T/R VRTN SERIAL I/F
PLL PCM I/F
C0029-E-02
8
1999/8
ASAHI
KASEI
[AK2305]
FUNCTIONAL DESCRIPTION
PCM INTERFACE
AK2305 supports the following types of format. One of those is selected by PCMIF0 and PCMIF1 registers. - Long Frame Sync(LF) - Short Frame Sync(SF) - GCI - IDL PCM data of both channels are multiplexed and interfaced through the common pins (DR0, DX0) in 2ch Multiplex I/F mode. But in 2ch Independent I/F mode of LF or SF, it is also available to interface through the independent pin(DR0/1,DX0/1) by channel. Register of PCM interface mode selection PCMIF1 PCMIF0 Interface 0 0 1 1 0 1 0 1 LF/SF (Non multiplex) LF/SF GCI IDL (2ch multiplex) (2ch multiplex) (2ch multiplex)
Frame sync FS0,FS1 FS0,FS1 FS0 FS0
Input pin DR0,DR1 DR0 DR0 DR0
Output pin DX0, DX1 DX0 DX0 DX0
Remarks
Reset
FRAME SYNC SIGNAL(Frame Sync : FS) Frame sync signal should be 8kHz clock. 8bits PCM data is accommodated in 1 frame (125us). Though only FS0 is required (FS1 isn't required) in the mode of GCI or IDL, both FS0 and FS1 are required in the mode of LF or SF. FIRST FS It is used as the input clock of PLL. PLL generates all timing in this IC from this signal. FS0 is assigned as First FS in the mode of GCI or IDL, and in the mode of LF or SF, it is assigned by the first FS register. 1stFS register 0 1 First FS FS0 FS1 Remarks
Reset
Note Keep supplying the first FS except for the state of all power down(PD="H"). If the first FS is not supplied, AK2305 loses timing; at a result, DTMFR and TONE GEN become not guaranteed to work normally. BCLK This clock decides the PCM data rate. See the following table of the relation between BCLK and PCM data rate. PCM I/F mode LF/SF/IDL GCI BCLK F 2F Rate of PCM data F F
C0029-E-02
9
1999/8
ASAHI
KASEI
[AK2305]
Long Frame Sync(LF) Short Frame Sync(SF)
AK2305 automatically decides whether Long Frame or Short Frame should be selected, by monitoring the high level period of First FS. Period of First FS ="H" more than 2 clock of BCLK 1 clock of BCLK INTERFACE TIMING <2ch Multiplex> PCM data of both channel are interfaced by the DX0 and DR0(DX1 and DR1 are not used) at the format of 8bits in the period of 1 frame(125us) which synchronizes with the FSn(n=0,1). In the period of 1frame, 64 time slots can be assigned at the maximum (in case of BCLK=4.096MHz). The number of the time slots is BCLK/64k. The time slot assignment of CH0 and CH1 is decided by FS0 and FS1. In the mode of LF and SF, second FS(not first FS) must be delayed or fast at least (8/BCLK) x n: (n=1 - 63) from the first FS. LongFrame
FS0 BCLK DX0 DR0
Don't care
Frame type LF SF
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
Don't care
ShortFrame
FS0 BCLK DX0 DR0
Don't care
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
Don't care
BCLK=4096kHz ( First FS = FS0 )
FS0 FS1 SLOT DX0 DR0 1
ch0 output ch0 input
2
3
ch1 output ch1 input
4
63
64
1
ch0 output ch0 input
2
3
ch1 output ch1 input
4
C0029-E-02
10
1999/8
ASAHI
KASEI
[AK2305]
INTERFACE TIMING PCM data of each channel are interfaced by each I/O pins(DX0 and DR0/DX1 and DR1) at the format of 8bits in the period of 1 frame(125us) which synchronizes with the FSn(n=0,1). The timing of FS0 and FS1 can be set at optionally as far as they synchronize with BCLK. NOTE) First FS and Second FS Only when BCLK=64kHz, it is possible to input the same clock to the first FS and the second FS. Except for 64kHz BCLK, 8 clock of BCLK x n (n=1-63 integral numbers) intervals of n slots are needed. BCLK=4096kHz ( First FS = FS0 )
FS0 FS1 SLOT DX0 DR0 DX1 DR1 1
ch0 output ch0 input ch1 output ch1 input
2
3
4
63
64
1
ch0 output ch0 input
2
3
4
ch1 output ch1 input
BCLK=64kHz(LF) ( FS0 and FS1 at the same timing, First FS = FS0 )
FS0,FS1 BCLK DX0 DR0 DX1 DR1 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4
BCLK=64kHz(LF) ( First FS = FS0 )
FS0 FS1 BCLK DX0 DR0 DX1 DR1 1 1 2 2 3 3 1 1 4 4 2 2 5 5 3 3 6 6 4 4 7 7 5 5 8 8 6 6 1 1 7 7 2 2 8 8 3 3 1 1 4 4 2 2 3 3 4 4
C0029-E-02
11
1999/8
ASAHI
KASEI
[AK2305]
GCI(General Circuit Interface)
Interface used for ISDN. This data format is as below. PCM data channel assignment for B1 and B2 is defined by SEL2B register. CH0,1selection SEL2B 0 1
CH0 B1 B2
CH1 B2 B1
Remarks Reset
Note: BCLK is twice the PCM data rate. BCLK is acceptable from 512kHz to 4096kHz.
INTERFACE TIMING <2ch Multiplex> PCM data of each channel is interfaced through DR0/DX0 pin in 8bits format. They are accommodated in 1 frame(125us) which synchronizes with FS0.
FS0 BCLK DX0 DR0
Don't care
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
Don't care
B1-CHANNEL(CH0)
B2-CHANNEL(CH1)
Not supported.
C0029-E-02
12
1999/8
ASAHI
KASEI
[AK2305]
IDL(Interchip Digital Link)
Interface used for ISDN. This data format is as below. PCM data channel assignment for B1 and B2 channel is defined by SEL2B register. CH0,1selection SEL2B 0 1
CH0 B1 B2
CH1 B2 B1
Remarks Reset
Note: BCLK is same as the PCM data rate. BCLK is acceptable from 256kHz to 4096kHz.
INTERFACE TIMING <2ch Multiplex> PCM data of each channel is interfaced through DR0/DX0 pin in 8bits format. They are accommodated in 1 frame(125us) which synchronizes with FS0.
FS0 BCLK DX0 DR0
Don't care
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
Don't care
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
Don't care
B1-CHANNEL(CH0)
B2-CHANNEL(CH1)
Not supported.
C0029-E-02
13
1999/8
ASAHI RESET
KASEI
[AK2305]
POWER ON RESET AK2305 automatically generates the internal reset pulse at the time of power on. Then all circuits are reset and internal registers are initialized. After reset operation, CODEC CH0/CH1 circuits start to be initialized. It takes 150ms(typ.), 330ms(max) from power on to completion of initialization. *)Output pins remain Hi-Z during the period in which the internal reset pulse is high(See page 5). The period of the reset pulse is about 20ms(typ), 200ms(max).
POWER-UP TIME FOR POWER ON RESET When power-up time is no longer than 50ms(=5tau:tau is time constant), Power On Reset works normally. When the time is longer than 50ms, Power On Reset is not available and no internal registers are initialized. All registers must be written.
RECOMMENDED START UP PROCEDURE The following start up procedure is recommended when AK2305 is going to power up.
Power up
Wait 200ms *In case of VDD rising time =50ms(=5tau)
- TNOE0,1=" L " - FSn=" L " - BCLK=" L " When 1stFS and BCLK are set to " L , " CODEC ch0,ch1 dose not interface with external devices.
Write data to the internal register through serial I/F
- Write data to the internal register before CODEC starts working.
Supply FSn and BCLK - CODEC Initialization starts. Wait 130ms - CODEC Initialization complete. CODEC starts working
C0029-E-02
14
1999/8
ASAHI
KASEI
[AK2305]
POWER DOWN
Power consumption is reduced in power down mode. In the power down mode, supply of current for analog circuits and clock for digital circuits, is stopped, and relating circuits are halted. There are two power down modes. - Power down for all circuits - Power down by block * In the power down mode, output pins of corresponded blocks turn to Hi-Z.(See page 4) POWER DOWN MODE SETTING Mode Circuits Pin/Registers Operation for "0"/"1" "0" : Normal "1" : Power down Note - Registers are not reset. - Serial I/F is available. - No need to supply FSn(n=0,1),BCLK. - Keep supplying first FS, even when CODEC CH0,1 are in power down mode (see page8). - Even when CODEC CHn(n=0,1) is in power down mode, the functions below are available: (1) AMPTn(n=0,1) Input/Output (2) TONEGEN0,1 Output From VRXn(n=0,1), TNOUT - Even when all these blocks are in power down mode; AMPT0/1, VR0/1R, AMPR0/1, VRTN, TONEGEN0/1, BGREF, Serial IF, PLL operate normally at all the time.
Pin
All circuits
All
PD
CODEC CH0 CODEC CH1 Block DTMF Receiver0 DTMF Receiver1
PDCH0
PDCH1 "0" : Normal "1" : Power down PDDT0
Note) Initial value of PDCHn, PDDTn(n=0,1) are "0".
CANCELLATION OF POWER DOWN : CODEC When power down mode for CODEC CH0/CH1 is cancelled, CODEC starts to be initialized. It takes 130mS(typ.).
Registers
PDDT1
C0029-E-02
15
1999/8
ASAHI
KASEI
[AK2305]
POWER DOWN MODE SETTING and POWER DOWN BLOCK POWER DOWN BLOCK PIN REGISTER AMPT0 VR0T Channel 0 AAF0 CODEC CH0 SMF0 VR0R AMPR0 AMPT1 VR1T Channel 1 AAF1 CODEC CH1 SMF1 VR1R AMPR1 PCM I/F TONEGEN 0 TONEGEN 1 VRTN DTMFR 0 DTMFR 1 PLL BGREF SERIAL I/F ALL BLOCK PD OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF CODEC CH0 PDCH0 CODEC CH1 PDCH1 CODEC CH0&1 PDCH0 PDCH1 CODEC CH0, DTMFR0 PDCH0 PDDT0 OFF OFF OFF OFF OFF CODEC CH1, DTMFR1 PDCH1 PDDT1
DTMFR0 PDDT0
DTMFR1 PDDT1
C0029-E-02
16
1999/8
ASAHI MUTE
KASEI
[AK2305]
PIN CONTROL The output on each channel can be muted independently by pin control. MUTEn (n=0,1) 0 Operation Normal Mute DXn pin (n=0,1) PCM data output High-Impedance VRXn pin (n=0,1) CODEC analog output AGND*
*)TONE circuits are avialable even if the mute operates.
Remarks
1
REGISTER CONTROL The output on each channel can be muted independently by register control. MTDXn (n=0,1) 0 Operation Normal Mute DXn pin (n=0,1) PCM data output High-Impedance VRXn pin (n=0,1) CODEC analog output* (MUTE0,1pin="0") Remarks Reset
1
*) MUTEn is given priority over MTDXn. Therefore, for instance, even when MTDXn is "1," output of VRXn is AGND if MUTEn="1." CH0 muted (MUTE0="1," MUTE1="0," MTDX0,1="0" : GCI mode)
FS0 BCLK DX0 DR0
Don't care B1-CHANNEL(CH0)
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
Don't care
B2-CHANNEL(CH1)
VRX0 : VRX1 :
CODEC CH0 analog output is always at AGND level. TONEGEN0,1output can be controlled by TNOE0,1 pin. CODEC CH1 analog output is the signal converted from the PCM data of CH1 input through DR0 pin. TONEGEN0,1 output can be controlled by TNOE0,1 pin.
C0029-E-02
17
1999/8
ASAHI
KASEI
[AK2305]
GAIN ADJUSTMENT
Analog input/output gain can be adjusted at the range from0 to -12dB (3dB/step*5steps) by register. VR register VRnT2 VRnR2 VRTN2 0 0 0 0 1
VRnT1 VRnR1 VRTN1 0 0 1 1 -
VRnT0 VRnR0 VRTN0 0 1 0 1 -
Gain 0 dB -3 dB -6 dB -9 dB -12 dB
Remarks Reset
*) This table is applicable to VR0T,VR0R,VR1T, VR1R ,and VRTN registers.
C0029-E-02
18
1999/8
ASAHI
KASEI
[AK2305]
DTMF RECEIVER
This circuit detects and decodes the DTMF signal and outputs the 4bits code. See the following table. Output code table Low Tone [Hz] 697 (n=0,1) DTO n0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
High Tone [Hz] 1209 1336 1477 1209
KEY 1 2 3 4 5 6 7 8 9 0 * # A B C D
DTO n3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
DTO n2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
DTO n1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
770
1336 1477 1209
852
1336 1477 1336
941 697 770 852 941 DECODED OUTPUT
1209 1477 1633 1633 1633 1633
Decoded DTMF signals are output at DTO00-03,10-13 pins through tri-state buffers. The outputs are enabled by DTOE pin. DTOE Input 0 1 DTO00-03, DTO10-13 Output Hi-Impedance Decoded Output
GUARD TIME SETTING Input Signal Available Time(tREC) and Inter Digit Pause Time(tID) can be settled by adjusting Guard Time as follows. Guard Time is adjusted by GTPn, GTAn(n=0-3.) Input Signal Available Time(tREC) Inter Digit Pause Time(tID) = Detecting Signal Time(tDP) + Guard Time(tGTP) = Detecting Signal-stop Time(tDA) + Guard Time(tGTA) 1ms - 121 ms 8ms
Range of adjusting Guard Time(tGTP, tGTA) Step of adjusting Guard Time(tGTP, tGTA)
Regarding the relation between GTPn / GTAn(n=0-3) and Guard Time, see the next page. Also the relation between Input Signal Available Time(tREC) and Inter Digit Pause Time(tID) is shown. C0029-E-02 19 1999/8
ASAHI
KASEI
[AK2305]
Relation between GTPn(n=0- 3) Register and GUARD TIME(tGTP) / Input Signal Available Time(tREC) GTP Register 2 1 0 tGTP[ms] typ 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 tREC[ms]=tGTP+tDP min typ max 6 12 15 14 20 23 22 28 31 30 36 39 38 44 47 46 52 55 54 60 63 62 68 71 70 76 79 78 84 87 86 92 95 94 100 103 102 108 111 110 116 119 118 124 127 126 132 135
tDP[ms]
min 5 typ 11 max 14
3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
tGTP default
Relation between GTAn(n=0- 3) Register and GUARD TIME(tGTA) / Inter Digit Pause Time(tID ) GTA Register 2 1 0 tGTA[ms] typ 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 tID[ms]=tGTA+tDA min typ max 1.5 5 9.5 9.5 13 17.5 17.5 21 25.5 25.5 29 33.5 33.5 37 41.5 41.5 45 49.5 49.5 53 57.5 57.5 61 65.5 65.5 69 73.5 73.5 77 81.5 81.5 85 89.5 89.5 93 97.5 97.5 101 105.5 105.5 109 113.5 113.5 117 121.5 121.5 125 129.5 tDA[ms] typ max 4 8.5
3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
min 0.5
tGTA default
NOTE tGTA in tables above are typical value. Regard the margin of 1ms.
C0029-E-02
20
1999/8
ASAHI
KASEI
[AK2305]
TONE GENERATOR
Generates two kinds of tone, 400Hz and 1300Hz. One of them is selected by TMDn register.
SELECTION OF TONE Selects 1 tone from 400Hz/1300Hz by TMDn register. Tone selection register TMDn 0 1 (n=0,1)
Tone frequency 400Hz 1300Hz
Remarks Reset
SELECTION OF OUTPUT PIN VRX0, VRX1, TNOUT is available for Tone output pin by S1-S9 switch. S1-S9 switch is controlled by each register. Tone output by switch controlling Output VRX0 circuits TONEGEN0 TONEGEN1 AUX S1 S2 S3
VRX1 S4 S5 S6
TNOUT S7 S8 S9
Register setting
Remarks
"0" : OFF "1" : ON
All "0" when reset
TONE OUTPUT ENABLE Inputting "1" to TNOEn, defined tone is output. Tone Output Enable TONEn Output States 0 1 AGND Tone
AUX INPUT
Input signal from external CPU/Tone generators. Signals are output on VRXn, TNOUT via VRnR, VRTN. Output signals are switched onto each pin by S3, S6, and S9 which are controlled by registers. (See "SELECTION OF OUTPUT PIN" above.) Must input with an external cap(>0.1uF.) Input impedance is 200k25%. C0029-E-02 21 1999/8
ASAHI
KASEI
[AK2305]
SERIAL INTERFACE
The internal registers can be read/written with SCLK, DATA, and CS pins. 1word consists of 14bits. The first 2bits are the instruction code which specifies read/write. The following 3bits specify the address. The rest of 8bits are for setting registers. B13 I1 B12 I0 B11 A2 B10 A1 Address (3bit) B9 A0 B8 * * B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 D0
Instruction code (2bit)
Data for setting internal registers (8bit)
*)Dummy bit for adjusting the I/O timing when reading data.
INSTRUCTION CODE I1 1 1 I0 0 1 Read/Write Read Write No action
Other codes
SCLK and WRITE / READ (1) Input data are loaded into the internal shift register at the rising edge of SCLK. (2) The rising edge of SCLK is counted after the falling edge of CS . (3) When CS is "L" and more than 14 SCLK pulses: [WRITE] Data are loaded into the internal register at the rising edge of the SCLK 14th pulse. [READ] DATA pin is switched to an input pin at the falling edge of the SCLK 14th pulse.
CS and WRITE / READ CANCELLATION (1) WRITE is cancelled when CS goes up before the rising edge of the SCLK 14th pulse. (2) READ is cancelled when CS goes up before the falling edge of the SCLK 14th pulse.
SERIAL WRITE / READ (SERIAL ACCESS) (1) CS must go up to "H" before the next access in successive access. (2) When the next access is going to be done , if CS remains to be "L", successive access can not be done.
C0029-E-02
22
1999/8
ASAHI
WRITE
KASEI
[AK2305]
Must goes up once
CS SCLK DATA
Z 1 2 3 4 13 14 Z
Goes up anytime after SCLK14th pulse
1
2
3
4
13
14 Z
1
1
0
0 Address "000"
0
*
D7
D1 D0 WRITE data to address"000"
1
1
0
1
0
*
D7
D1 D0
Instruction code
WRITE at the rising edge of SCLK 14th pulse
Instruction Address code "010" Z
WRITE data to address"010" DATApin : Input Status (Hi-Z)
WRITE - CANCELLATION WRITE cancellation
CS SCLK DATA
Z 1 2 3 4 13 14 Z 1 2 3 4 13 14 Z
1
1
0
0 Address "000"
0
*
D7
D1 WRITE data to address"000"
D7
1
1
0
1
0
*
D7
D1 D0
Instruction code
WRITE is not executed
Instruction code
Address "010"
WRITE data to address"010"
WRITE - SERIAL ACCESS CS SCLK DATA
Z 1 2 3 4 13 14 1 Z 2 3 4 13 14 Z
1
1
0
0 Address "000"
0
*
D7
D1 D0 WRITE data to address"000"
1
1
0
1
0
*
D7
D1 D0
Instruction code
Instructi on code Execute
Address "010"
WRITE data to address"010" Not Execute
C0029-E-02
23
1999/8
ASAHI
READ
KASEI
[AK2305]
Must goes up once
1
3
13
1 Z
3
13
DATA
1 Instruction code
0 Address "000"
0
D7
D1 READ data from address"000"
0 Instruction code
1 Address "010"
D0 READ data from address"010"
READ - OUTPUT PERIOD OF DATA PIN CS SCLK DATA
Z 1 2 3 4 Z 13 14 Z 1 1 2 0 3 0 4 1 0 Z * D7 13 14 Z
1
0
0
0
0
D7
D1 D0
D1 D0
Instruction code
Address "000"
READ data from address"000"
Instruction code
Address "010"
READ data from address"010"
READ PERIOD: Till the earlier edge of either CS rising up or SCLK 14th pulse falling.
READ - SERIAL ACCESS CS SCLK DATA
Z 1 2 3 4 13 14 1 Z 2 3 4 Z READ data from address"010" Not Execute 13 14
1
0
0
0 Address "000"
0
Z *
D7
D1 D0 READ data from address"000"
1
0
0
1
0
Instruction code
Instruction code Execute
Address "010"
DISCORD OF INSTRUCTION CODE
CS SCLK DATA
1 2 3 4 13 14 Z 1 0 2 1 3 0 4 1 0 13 Z WRITE/READ is not executed 14
0
0
0
0
0
Other codes (not Instruction code)
Address "000"
WRITE/READ is not executed
Other codes (not Instruction code)
Address "010"
C0029-E-02
24
1999/8
ASAHI
KASEI REGISTER
[AK2305]
REGISTER MAP
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A2 0
A1 0
A0 0
* *
D7 -
D6 VR0T2
D5 VR0T1
D4 VR0T0
D3 -
D2 VR0R2
D1 VR0R1
D0 VR0R0
0
0
1
*
-
VR1T2
VR1T1
VR1T0
-
VR1R2
VR1R1
VR1R0
0
1
0
*
-
S9
S8
S7
-
VRTN2
VRTN1
VRTN0
0
1
1
*
-
S6
S5
S4
-
S3
S2
S1
1
0
0
*
PCMIF1
PCMIF0
SEL2B
1stFS
PDDT1
PDDT0
PDCH1
PDCH0
1
0
1
*
-
-
-
ALAWN
MTDX1
MTDX0
TMD1
TMD0
1
1
0
*
GTA3
GTA2
GTA1
GTA0
GTP3
GTP2
GTP1
GTP0
*) Dummy Bit Note) All registers are available for write/read.
INITIALIZATION OF REGISTERS Only at POWER ON RESET, registers are initialized. When POWER ON RESET is not used, all registers should be set through a serial interface.
C0029-E-02
25
1999/8
ASAHI
KASEI
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Receive gain adjustment on ch0 0 to -12dB by 3dBstep 000: 0dB 1xx: -12dB Not used Transmit gain adjustment on ch0 0 to -12dB by 3dBstep 000: 0dB 1xx: -12dB Not used Dummy bit Receive gain adjustment on ch1 0 to -12dB by 3dBstep 000: 0dB 1xx: -12dB Not used Transmit gain adjustment on ch1 0 to -12dB by 3dBstep 000: 0dB 1xx: -12dB Not used Dummy bit Gain adjustment of tone output 0 to -12dB by 3dBstep 000: 0dB 1xx: -12dB Not used Switch regulation for tone output 0: Tone OFF 1: Tone ON Not used Dummy bit Switch regulation for tone output 0: Tone OFF 1: Tone ON Not used Switch regulation for tone output 0: Tone OFF 1: Tone ON Not used Dummy bit
[AK2305]
Refer to
FUNCTION OF REGISTER Address Bit Name 000 0 VR0R0 1 VR0R1 2 VR0R2 3 4 VR0T0 5 VR0T1 6 VR0T2 7 8 001 0 VR1R0 1 VR1R1 2 VR1R2 3 4 VR1T0 5 VR1T1 6 VR1T2 7 8 010 0 VRTN0 1 VRTN1 2 VRTN2 3 4 S7 5 S8 6 S9 7 8 011 0 S1 1 S2 2 S3 3 4 S4 5 S5 6 S6 7 8 -
18
18
21
C0029-E-02
26
1999/8
ASAHI
KASEI
Bit 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 Name PDCH0 PDCH1 PDDT0 PDDT1 1stFS SEL2B PCMIF0 PCMIF1 TMD0 TMD1 MTDX0 MTDX1 ALAWN GTP0 GTP1 GTP2 GTP3 GTA0 GTA1 GTA2 GTA3 Default 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Function CODEC ch0,1 Power down control 0: Power ON 1: Power OFF DTMF Receiver 0,1 Power down control 0: Power ON 1: Power OFF First FS select 0: FS0 1: FS1 PCM data channel assignment 0: CH0->B1 PCM interface select Multiplex/Non Multiplex Dummy bit TONEGEN 0,1 tone frequency select 0: 400Hz 1: 1300Hz PCM output(DX0,1pin) Mute 0: PCM OUT 1: PCM MUTE A-law/u-law select 0:A-law 1:u-law Not used Dummy bit DTMF Receiver Guard Time tGTP setting
[AK2305]
Refer to 15 9 12 9
Address 100
101
21 17 8
110
20
DTMF Receiver Guard Time tGTA setting Dummy bit
20
C0029-E-02
27
1999/8
ASAHI
KASEI
[AK2305]
BSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltages Digital Power Supply Min DVDD AVDD DVSS Max 6.5 V V V V V C
Digital Input Voltage TD Analog Input Voltage TA Input current (except power supply pins) IN Storage Temperature Tstg Note 1) All voltages with respect to ground. AVSS=
-0.3 -0.1 -0.3 -0.3
10 125 =0V
Normal operation is not guaranteed at these extremes.
R
OPERATING ONDITIONS
Typ 5.0 5.0 8 Units V C
Parameter Min Power Supplies Analog power supply 4.75 Digital power supply DVDD Ambient Operating Temperature Ta Frame Sync Frequency FS0,FS1 Note 1) If DVDD is greater than AVDD, then IDD will increase ) All voltages reference to ground AVSS= =0V
AVDD 85
LECTRICAL C
Unless otherwise noted, guaranteed for AVDD=DVDD=+5V +/- 5%, Ta = - DC Characteristics Parameter Power Consumption ~ +85 o , FS0,FS1=8kHz
Conditions
DD1
Min
Max 105 60 78.8
Units
PDD Output High Voltage1 VOH
1
Output Low Voltage V (CMOS level) V (TTL level) V (TTL level) Ii Input Capacitance Io Current
All outp unloaded PDCH0,1 PDDT0,1=1,0 All o ut unload IOH mA Except for DTOn0-n3(n=0,1) I =1.6mA 2.0
V 0.4 V V 0.8 10 -10 +10 5 +10 V A pF A
C0029-E-02
1999/8
ASAHI
CODEC
KASEI
[AK2305]
Absolute Gain Conditions Input: 0dBm0@1020Hz -0.6 Input: 0dBm0@1020Hz -0.6 3.14dBm0 Typ Units Vrms dB Vrms dB Vrms
Parameter Transmit Gain Tracking Error 1020Hz Tone Receive Gain Tracking Error -10dBm0
-55dBm0 ~ -50dBm0 -40dBm0 ~ -55dBm0 -50dBm0 ~ -40dBm0 3dBm0
Min -1.2 -0.2 -0.4
Max 0.4 1.2 0.2 dB
Parameter Transmit Frequency Response
0.05kHz 0.2kHz 0.3 3.0kHz 3.4kHz Relative to: ~ 3.4kHz 4.0kHz
Min -
Max -26 0.15 0 -14
-0.15 -
0 -
Distortion Conditions 1020Hz Tone ~ -30dBm0 -40dBm0 ~ ~ -30dBm0 -40dBm0 ~ 25 36 25 36 -6dBm@860Hz,1380Hz -Law, Psophometric Weighted for A-Law Typ Units dB dB dB dB dB
1020Hz Tone
Transmit Receive
C0029-E-02
1999/8
ASAHI
KASEI
Conditions f =1600Hz f =500Hz 600Hz f =600Hz 1000Hz f =1000Hz 2600Hz f =2600Hz ~ f =2800Hz 3000Hz f =500Hz ~ f =1000Hz ~ f =1600Hz ~ ~2800Hz ~3000Hz Typ -40 -30 -
[AK2305]
Max 560 220 145 75 us 155 450 -
Parameter Transmit Delay, Absolute Transmit Delay, Relative
us
Receive Delay, Absolute
us 125 175
Relative to f=1600Hz
Parameter Idle Channel Noise O Idle Channel Noise 2) O Noise, Single Frequency PSRR, Transmit
Conditions u A-law, Psophometric u A-law, Psophometric f=0 100kHz
Typ 5 -
Max 10 dBrnC0 -80 dBrnC0 -80 -53 dB
f=0 50kHz AVDD=DVDD=5V 100mVop ~ Spurious Out-of-Band Signal 4.6 7.6kHz at VRX Output 0.3 3.4kHz ~ 8.4 100kHz Note 1) Analog Input = Analog Ground Note 3) Not tested in production. Parameters guaranteed by design.
40 -
-
-
dB
Parameter Transmit to Receive Receive to Transmit Transmit to Transmit Receive to Receive
Min -
Max -75 -75 -75 -75
Intrachannel Crosstalk Conditions 0dBm0@VFXIN, Idle PCM code 0dBm0 code level, VFXIN = 0 Vrms Typ Units dB dB
C0029-E-02
1999/8
Parameter Input Leakage Current Input Resistance Load Resistance Load Capacitance Output
Min -100 -
Max +100 M k pF 10
Parameter Output Voltage Load Resistance Load Capacitance Output
Min 2.3
Max 2.5 k pF 3.6 10
Parameter Input Leakage Current Input Resistance Load Resistance Load Capacitance Output
Min -100 -
Max +100 M k pF 10
VR0T,VR0R,VR1T,VR1R,VRTN Pin Step margin
Volume
Min -0.5
max dB
Parameter TNOUT AUX Abcolute gain (Relative to output signal 1kHz input) TNOUT TNOUT
Conditions VRTN=0dB
typ
Unit dBm
200 VRTN=0dB VRTN=0dB 0 0
k dB dB
C0029-E-02
Tone Generator Conditions Signal 1300Hz -11 Out of band noize level 4k-8kHz P-40 P-60 Note) dBm = decibels above or below a reference power of 1mW into a 600 P = output level of in band transmit signal. 381 1300 -9 dB typ 419 Hz Units
Parameter Valid Input Signal Levels signal) Note3,6,8 Frequecy Deviation accept Frequecy Deviation Reject Third Tone Tolerance Noise Tolerance Dial Tone Tolerance Input Impeedance Note2)Both tones of the composite signal have equal amplitudes. Note4)Bandwidth limited to 3kHz Gaussian noise. Note6)For error rate of better than 1 in 10,000. Note8)Twist = high tone / low tone dBm = decibels above or below a reference power of 1mW into a 600
min -19 10
Max dBm

-16 -12 -17 500
C0029-E-02
ASAHI
KASEI
[AK2305]
Parameters t Tone Absent Detection Time t Tone Duration Reject(*1) Interdigit Pause Accept(*1) t t t t t
R ID O DA
Condition 5
Typ 14 4 48 37
Units ms
s
ms ms us us us 40 ns
DTOE=5V,unloaded DTOE=5V,unloaded DTOE=5V,unloaded R =10k, C =50pF
10 GPAn
Output Data Disable(DTOE to DTO) PTD L L GTPn, (n=0-3) are default. Adjustable by setting See p.19 & p.20.
tREJ
DTINx RegisterGTP Internal Counter tGTP ,tGTA
tREC tDP
TONE #n
tID tDA
TONE #n+1
tDO
tGTP
RegisterGTA
tGTA
tPQ
DTOxx STDx DTOE DECODED TONE #n-1 DECODED TONE #n
Hi-Z
DECODED TONE #n+1
tPSTD tQSTD tPTD tPTE
Figure 1 : DTMF Receiver Timing
33
1999/8
ASAHI
KASEI
[AK2305]
Timing Specification Unless otherwise noted, the specification applies for TA = -40 to +85oC, DVDD = AVDD = 5V5%,DVSS = AVSS = 0V and FS0,FS1 = 8kHz. All timing parameters are measured at VOH = 2.0V and VOL =0.7V. Lomg Frame,Short Frame,GCI, IDL Timing Parameter FS Frequency BCLK Frequency BCLK Pulse Width High BCLK Pulse Width Low Rising Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1) Falling Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1) Hold Time: BCLK Low to FS High Setup Time: FS High to BCLK Low Setup Time: DR to BCLK Low Hold Time: BCLK Low to DR Delay Time: BCLK High to DX valid Long Frame Hold Time: 2nd period of BCLK Low to FS Low tHBFL 40 60 10 1 60 ns ns ns
BCLK Symbol
Min 64 80 80
Typ 8
Max 4096
Unit Ref fig kHz kHz ns ns
1/tPF 1/tPB tWBH tWBL tR tF tHBF tSFB tSDB tHBD (Note1) tDBD
40 40 40 70 40 40 60
ns ns ns ns ns ns ns
Fig.2 Fig.3 Fig.4 Fig.5
Delay Time: FS or BCLK High, whichever is later,to DX valid t (Note1) DZFL Delay Time: FS or BCLK Low, whichever is later, to DX HightDZCL Z (Note1) FS Pulse Width Low Short Frame Hold Time: BCLK Low to FS Low Setup Time: FS Low to BCLK Low Delay Time: BCLK Low to DX High-Z GCI BCLK Frequency Delax Time: Second BCLK Low to DX High-Z Setup Time: DR to Second BCLK High Hold Time: Second BCLK High to DR IDL BCLK Frequency Note1) When with 150pF cap, and two LSTTL operating. C0029-E-02 34 1/tPB 1/tPB tDZCG tSDBG tHBDG tHBFS tSFBS (Note1) tDZCS tWFSL
Fig.2
40 40 10 60
ns ns ns Fig.3
512 10 40 40
4096 60
kHz ns ns ns Fig.4
256
4096
kHz
Fig.5
1999/8
ASAHI
KASEI
[AK2305]
tFB
tRB
tWBL
tWBH
t PB
BCLK
tSFB tHBFL
FSn (n=0 or 1) DXn
tHBF
tDZFL
tDBD
tDZCL 7 8
tDZCL
MSB
2
3 tSDB
4 tHBD
5
6
DRn
MSB
2
3
4
5
6
7
8
FSn (n=0 or 1)
tPF tWFSL
Figure2 :
PCM Interface Timing < Long Frame >
t FB
t RB
tWBL
tWBH
tPB
BCLK
t SFB tHBFS
FSn (n=0 or 1) DXn
t HBF
tSFBS tDBD MSB 2 3 tSDB 4 tHBD 5
tDBD
tDZCS
6
7
8
DRn
MSB
2
3
4
5
6
7
8
Figure3 :
PCM Interface Timing < Short Frame >
C0029-E-02
35
1999/8
ASAHI
KASEI
[AK2305]
FS0
tPBG 12345 6 7 8 9 10 11 12 13 14 15 16 tWBH
BCLK
tDBD tDZCG 3 4 5 tHBDG tSDBG 6 7 8 MSB 2 3 4 tWBL
DX0
MSB
2
5
6
7
8
DR0
MSB
2
3
4
5
6
7
8
MSB
2
3
4
5
6
7
8
BCLK
tSFB tHBFS
FS0
tHBF tDZFL
DX0
1
2
3
Figure4 :
PCM Interface Timing < GCI >
tPBI
tWBH
BCLK
1 t SFB
2
3
4
5
6
7
8 tWBL
FS0
tHBF tHBFS tDBD tDZCS 3 4 5 tHBD tSDB 6 7 8 MSB 2 3 4 5 6 7 8
DX0
MSB
2
DR0
MSB
2
3
4
5
6
7
8
MSB
2
3
4
5
6
7
8
Figure5 :
PCM Interface Timing < IDL >
C0029-E-02
36
1999/8
ASAHI
KASEI
[AK2305]
Serial Interface Timing Parameter SCLK Frequency SCLK Pulse Width High SCLK Pulse Width Low
CS Pulse Width Low Symbol
Min
Typ
Max 4
Unit Ref fig MHz ns ns SCLK ns ns Fig.6
1/tPSCLK tW SH tW SL tWCL tHCS tSCS tR tF 40 40 14 80 40
Hold Time: SCLK High to CS Low Setup Time: CS Low to SCLK High Rising Time: CS ,SCLK Falling Time: CS ,SCLK WRITE Setup Time: DATA to SCLK High Hold Time: SCLK High to DATA Hold Time: SCLK Low to CS High READ Delay Time: SCLK Low to DATA pin drive Delay Time: SCLK Low to DATA valid Delay Time: SCLK Low to DATA High-Z Delay Time: CS High to DATA High-Z
CS Pulse Width High
100 100
ns ns
tSDC tHDC tHCS2
40 40 0
ns ns ns Fig.6
tDVD tDDD tDZSD tDZCD tWCH
0 60 0 0 40 60 60
ns ns ns ns ns
Fig.7
Fig.8
C0029-E-02
37
1999/8
ASAHI
KASEI
tWCL
[AK2305]
CS
tWSH tWSL tPSCLK tF tR tHCS2
tHCS
SCLK
tHD tSCS tSDC
DATA
I1
I0
A2
A1
A0
*
D7
D6 - D1
D0
Figure6 :
Serial Interface Timing < WRITE >
tWCL
CS
tWSH tWSL tPSCLK tF tR tHCS2
tHCS
SCLK
tHD tSCS tSDC tDDD Z I0 A2 A1 A0 D7 D6 - D1 D0 tDVD
DATA
I1
Figure7 :
tWCH
Serial Interface Timing < READ >
CS
SCLK
tDZSD tDZCD Z Z
DATA
D1
D0
I1
I0
D0
Figure8 :
Serial Interface Timing < READ >
C0029-E-02
38
1999/8
ASAHI KASEI
APPLICATION CIRCUIT EXAMPLE
[AK2305]
Analog input circuit(AMPT0,1) AK2305 has an op-amp at analog input of each channel. Each op-amp can be used as a gain adjustment. Op-amp can be used as an inverting amplifier. Feedback resistor must be 10k or larger.
AK2305 GSXn R2 C1 R1 VFXn (n=0,1)
C1=0.47uF R1=R2=33kOhm
BGREF
Analog output circuit(AMPR0,1) AK2305 has an op-amp at analog input of each channel. Each op-amp can be used as a gain adjustment. Op-amp can be used as an inverting amplifier. Feedback resistor must be 10k or larger.
AK2305 GSRn R1 VFRn R2 VRXn SMFn BGREF (n=0,1)
R1=R2=33kOhm
AUX INPUT An external tone is input to AUX through an external capacitance of more than 0.1uF.
AK2305 AUX C
C0029-E-02
39
1999/8
ASAHI KASEI
DTIN0, DTIN1 INPUT There are the following 2 cases in case of that DTMF tone is input through DTIN0,DTIN1. (1)DTMF tone is output from AMPT0,AMPT1 included AK2305 Connect GSXn with DTINn directly.
AK2305 GSXn
[AK2305]
DTINn
(2) DTMF tone is output from an external amplifier DTMF tone is input to DTIN0,DTIN1 through an external capacitance of more than 0.1uF.
AK2305 DTIN0 DTIN1 C
Analog ground stabilization capacitor An external capacitor of more than 0.1uF should be connected between VREF and AVSS to stabilize analog ground (VREF).
AK2305 VREF C +
PLL Loop filter capcitor An external capacitor of more than 0.22uF should be connected between LPC and AVSS.
AK2305 LPC C +
C0029-E-02
40
1999/8
ASAHI KASEI
[AK2305]
Power Supply To attenuate the power supply noise, connect capacitors between AVDD and AVSS, and DVDD and DVSS, as shown below.
AK2305 AVDD C1 AVSS + C2 C1=C3=0.1uF C2=C4=10uF
DVDD C3 DVSS
+
C4
To use the same supply for both digital and analog power supply (DVDD and AVDD), insert 10 resistor between AVDD and DVDD. AVSS and DVSS must be separated on the board, and connected them at power supply unit. AK2305 AVDD C1 AVSS R1 DVDD C3 DVSS Ground of Power Supply Unit + C4 C1=C3=0.1uF C2=C4=10uF R1=10 Ohm + C2
C0029-E-02
41
1999/8
ASAHI KASEI
[AK2305]
PACKAGING INFOMATION
- 48pin LQFP Marking (1) Pin#1 indication (2) Date Code: 5 digit XXXXX (3) Marketing Code: AK2305 (4) AKM Logo
AKM
AK2305
XXXXX JAPAN
Outline Dimensions
9.00.2 7.0 36 37 25 24 1.7MAX
0.10 0.100.07
48 1 0.190.05 12
13
9.00.2
0.50
7.0
0.170.05
0.500.2
0~10
C0029-E-02
42
1999/8
ASAHI KASEI
[AK2305]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
C0029-E-02
43
1999/8

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